Reconfigurable Architectures for Embedded Systems

Application-specific circuits are used to migrate computer systems from workstations to handheld devices that need real-time performance within the budget for physical size and energy dissipation. However, these circuits are inflexible as any modification requires redesign and refabrication, which is both expensive and time-consuming considering the complexity of recent embedded platforms. Therefore, reconfigurable architectures that can be dynamically reconfigured and reused over several platforms have been suggested, and they have proven to provide high performance in a wide range of applications. This thesis focuses on two important topics when designing reconfigurable embedded systems: coarse-grained reconfigurable architectures and system level architectural exploration. It is argued that embedded systems that require programmable hardware acceleration of regular computation intensive kernels with word-level arithmetic should utilize coarse-grained reconfigurable architectures. It is also argued that design of these complex systems should be performed with tools for efficient modeling, simulation, and architectural exploration in order to analyze and tune design parameters before a chip is fabricated. This thesis presents two different coarse-grained reconfigurable architectures and a modeling and exploration environment to build and explore complete reconfigurable computing platforms. The first reconfigurable architecture consists of a number of locally interconnected processing elements and memory banks. The processing elements are configured into customized datapaths and the memory banks are used to move data back and forth between datapath and memory at high data rates. The reconfigurable architecture was integrated as a coprocessor and used to accelerate the G.723.1 speech codec. It is shown that the number of used clock cycles is reduced with 83% compared to processor only execution. The second reconfigurable architecture is built as an array of small instruction set processors and memory blocks, which are interconnected with local dedicated wires and a global hierarchical routing network. To address efficient architectural exploration, a SystemC exploration environment with user-interactive control is presented. The reconfigurable architecture is described as a scalable and parameterizable SystemC transaction level model. To evaluate a complete system, models of instruction set processors, busses, and memories have been developed.